Test Pattern Generation Using Pseudorandom Bist
نویسنده
چکیده
Pseudorandom built-in self test (BIST) generators have been widely utilized to test integrated circuit and systems. In this Project an accumulator-based-3 weight test pattern generation scheme is presented and proposed scheme generates set of test patterns with weights 0, 0.5 and 1. These accumulators are mostly found in current VLSI chips and that the scheme can be efficiently to drive the hardware of BIST pattern generation. The hardware requirements for this project are FPGA SPARTAN 3 and the software which are used as Modelsim and Xilinx . Finally test patterns are produced for 5bit and c880 testbench circuits.
منابع مشابه
Low Power Bist Implementation of Test Pattern Generation Based on Accumulator
The hardware overhead and fault coverage of a circuit is an important problem in integrated circuits and systems. To overcome this problem pseudorandom built-in-self-test (BIST) generators have been widely utilized to test integrated circuits and systems. A Pseudorandom pattern generator (PRPG) is used for generating test patterns (TPG). A weighted Pseudorandom built-in-self-test (BIST) schemes...
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